1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a complementary metal oxide semiconductor field effect transistor (CMOS FET).
2. Description of the Related Art
A CMOS device generally consists of an n-channel transistor (i.e., NMOS FET) utilizing electron carriers and a p-channel transistor (i.e., PMOS FET utilizing hole carriers, which transistors are interconnected, as shown in FIG. 1, to form a basic gate of a logic circuit. The CMOS gate has advantages such as low power consumption, high degree of integration, large noise margin, and large fan-out and is used in a highly integrated memory device such as a silicon DRAM.
Usually, a silicon (Si) semiconductor is used as the material for the CMOS device, as the electron mobility .mu..sub.e in Si is approximately 1500 cm.sup.2 /V.sec, and the hole mobility .mu..sub.h is approximately 450 cm.sup.2 /V.sec, which is one third of the electron mobility. Accordingly, the switching speed of the PMOS FET is slower than that of the NMOS FET, and thus restricts the switching speed of the CMOS device as a whole. Furthermore, to bring the current driving capability of the PMOS FET to the same level as that of the NMOS FET, the gate width of the PMOS FET must be made twice or three times as large as that of the NMOS FET because of the difference of carrier mobility, so that the area occupied by or the size of the PMOS FET is increased, and this limits an increase of the density of an integrated circuit using CMOS gates. Therefore, to increase the current driving capability and the switching speed of the CMOS gate, the switching speed of the PMOS FET must be increased; namely, a PMOS FET having an increased hole mobility must be provided.
Among known semiconductor materials, Ge and InSb have a high hole mobility. The electron mobility .mu..sub.e and hole mobility .mu..sub.h of Ge and InSb at a room temperature are shown in the following table.
______________________________________ Electron Hole Semiconductor Mobility Mobility Material cm.sup.2 /V .multidot. sec cm.sup.2 /V .multidot. sec ______________________________________ Ge 3900 1900 InSb 80000 1250 ______________________________________
InSb has a narrow forbidden band (energy gap) of 0.17 eV and it is difficult to produce an element operating at a room temperature by using InSb. Research has been made into the production of a p-channel transistor (PMOS FET) using Ge, but a good quality and stable oxide layer can not be formed on Ge. Therefore, although a Ge p-channel transistor can be produced (e.g., cf. JP-A (Kokai)-No. 58-61675 and JP-A-No. 62-54459) it can not be used in practice due to a large surface leakage current thereof, and further, it is difficult to carry out a surface treatment of Ge.
Crystal growth technology has made tremendous progress recently; for example, using a molecular beam epitaxy (MBE) method, a Si.sub.1-x Ge.sub.x mixed crystal can be grown on silicon (for example, cf. T. P. Pearsall et al., 1st Int. Symp. on Si MBE, 1985; H. Daembkes et al., IEDM. 1985; and T. Sakamoto, Researches of the Electrotechnical Laboratory, No. 875, Dec. 1986, pp. 112-121).
A p-channel transistor using a two-dimensional hole gas generated at an interface of a heterojunction of Si and Si.sub.1-x Ge, has been proposed (T. P. Pearsall et al., IEEE Electron Device Letters, Vol. EDL-7, No. 5, May 1986, pp. 308-310). This proposed transistor comprises, as shown in FIG. 2, a p-silicon (Si) substrate 51, an i-Ge.sub.0.2 Si.sub.0.8 layer 52 formed on the Si substrate, a p-Si layer 53 formed on the GeSi layer 52, an insulating (SiO.sub.2) layer 54, p.sup.+ -doped regions (source region 55 and drain region 56), a source electrode 57, a drain electrode 58, and a gate electrode 59. In this case, only the Si layer 53 is doped with p-type impurities (i.e., a modulation doping technique is adopted), the two-dimensional hole gas is generated in the GeSi layer 52 by feeding holes (carriers) from the Si layer 53 to the GeSi layer 52, and is controlled by a gate voltage applied to the gate electrode 59. The proposed transistor (FIG. 2) is a p-channel MODFET (Modulation Doped field-effect transistor) in which the Si layer 53 is doped with a large quantity of p-type impurities, and therefore, when an n-channel transistor must be formed together with the p-channel transistor for a complementary FET, a substrate structure suitable for the formation of the n-channel transistor must be first formed, a portion of the substrate removed by selective etching, and the Ge.sub.0.2 Si.sub.0.8 layer and the Si layer of FIG. 2 then a region newly developed to replace the rem portion. Namely, in this case, a semiconductor region for the n-channel transistor and another semiconductor region for the p-channel transistor must be formed (epitaxially grown), and therefore, the production process for the complementary FET becomes complicated.